Within the integrated circuit industry there is a continuing effort to increase integrated circuit speed as well as device density. As a result of these efforts, there is a trend towards using flip chip technology when packaging complex high speed integrated circuits. Flip chip technology is also known as control collapse chip connection (C4) packaging. In C4 packaging technology, the integrated circuit die is flipped upside down. This is opposite to how integrated circuits are packaged today using wire bond technology. By flipping the die upside down, ball bonds may be used to provide direct electrical connections from the bond pads directly to the pins of the package.
In the following discussion reference will be made to a number of drawings. The drawings are provided for descriptive purposes only and are not drawn to scale.
FIG. 1A illustrates integrated circuit packaging 101 which utilizes wire bonds 103 to electrically connect integrated circuit connections in integrated circuit die 105 through metal interconnects 109 to the pins 107 of package substrate 111. With the trend towards high speed integrated circuits, the inductance generated in the wire bonds 103 of the typical integrated circuit packaging 101 becomes an increasingly significant problem.
FIG. 1B illustrates C4 packaging 151 with the integrated circuit die 155 flipped upside down. In comparison with the wire bonds 103 of FIG. 1A, the ball bonds 153 of C4 packaging 151 provide more direct connections between the integrated circuit die 155 and the pins 157 of package substrate 161 through metal interconnects 159. As a result, the inductance problems associated with typical integrated circuit packaging technologies that use wire bonds are minimized. Unlike wire bond technology, which only allows bonding along the periphery of the integrated circuit die, C4 technology allows connections to be placed anywhere on the integrated circuit die surface. This leads to very low inductance and better power distribution to the integrated circuit which is another major advantage of C4.
A consequence of the integrated circuit die 155 being flipped upside down in C4 packaging 151 is that access to internal nodes of the integrated circuit die 155 for testing purposes has become a considerable challenge. In particular, during the silicon debug phase of a new product that is designed to be packaged into C4, it is often necessary to probe electrical signals from internal nodes of the chip, insitu, while the chip is packaged in its native C4 packaging environment. During the debug process it is often necessary to probe certain internal nodes in order to obtain important electrical data from the integrated circuit. Important data include measuring device parameters such as, but are not limited to, voltage levels, timing information, current levels and thermal information.
Present day debug process for wire bond technology is based on directly probing the metal interconnects on the chip front side with an electron beam (E-beam) or mechanical prober. Typical integrated circuit devices have multiple layers of metal interconnects and it is often difficult to access nodes that are buried deep in the chip. Usually other tools such as plasma etchers and focused ion beam systems must be used to mill away the dielectric and or metal above the node to expose nodes for probing .
With C4 packaging technology, however, this front side methodology is not feasible since the integrated circuit die is flipped upside down. As illustrated in FIG. 1B, access to the metal interconnects 159 for the purpose of conventional probing is obstructed by the package substrate 161. Instead, the P-N junctions forming the diffusion regions 163 of the integrated circuit are accessible through the back side of the silicon substrate of integrated circuit die 155. There are a number of potential optical-based applications that can be used to debug C4 mounted semiconductor devices. FIG. 2 illustrates a prior art method used to probe active diffusion regions in integrated circuits. In the setup shown in FIG. 2, an integrated circuit device 231 includes an active region 239 and non active region (metal) 241. An infrared laser 221 is positioned to focus a laser beam 223 through a beam splitter 225, a birefringent beam splitter 227 and an objective lens 229 through the back side of the integrated circuit device 231 on the diffusion region 239 and metal 241. As shown in FIG. 2, birefringent beam splitter 227 separates the laser beam 223 into two separate laser beams, a probe laser beam 235 and reference laser beam 237. Both probe laser beam 235 and reference laser beam 237 are reflected from active region 239 and metal 241, respectively, back through objective lens 229 into birefringent beam splitter 227. Probe laser beam 235 and reference laser beam 237 are then recombined in birefringent beam splitter 227 and are guided into detector 233 through beam splitter 225.
By operating the integrated circuit device 231 while focusing probe laser beam 235 on active region 239 and reference laser beam 237 on metal 241, timing waveforms may be detected with detector 233 through the silicon substrate of device 231. Detection is possible due to the plasma-optical effect in which the refractive index of a region of charge is different to a region with no charge. The application of a bias causes the charge, and hence the refractive index, in the probed region to be modulated whereas the refractive index of the region under the reference beam is unaltered. This results in phase shift between probe beam 235 and reference beam 237. Accordingly, by measuring the phase difference between the reflected reference beam 237 and probe laser beam 235, detector 233 is able to generate an output signal 241 that is proportional to the charge modulation caused by operation of the P-N junction region under the probe. This optical measurement can then be combined with conventional stroboscopic techniques to measure high frequency charge and hence voltage waveforms from the P-N junction region 239.
Other optical-based applications, such as optical-based imaging through silicon using an infrared laser scan microscope, thermal mapping, temperature probing, etc., can be used in the testing of integrated circuits by focusing a light source onto a portion of the circuit (e.g., a diffusion area, P-N junction, metal contact, metal interconnect, etc.) and monitoring the reflected light. For instance, thermal mapping or temperature probing may be accomplished by directing a laser beam onto a metal interconnect, or other portion of the integrated circuit, and detecting the index of refraction change due to temperature fluctuations in the integrated circuit.
Another type of optical-based testing method involves the use of an infra-red camera 350 that is positioned to detect photon emissions 302 from the back side surface 304 of a semiconductor substrate 305 containing an integrated circuit device 306, as illustrated in FIG. 3. The detection of back side photon emissions is useful in determining a variety of circuit related defects, such as, but not limited to, impact ionization, shorts, hot carrier effects, forward and reverse bias junctions, transistors in saturation, and gate oxide breakdown.
Due to high doping concentrations found in present day semiconductor devices, however, there is a significant reduction in the transmission of energy traveling through the highly doped semiconductor substrate. Reflections at the semiconductor-air interface also cause a significant reduction in the transmission of light through the back side of the semiconductor substrate. As shown in FIG. 4, the intensity of an incident infrared beam 402 directed into a semiconductor substrate 410 by a laser 400 is reduced as the beam passes through the semiconductor back side surface 412. As shown in FIG. 4, a portion of the beam's energy is directed into the substrate while another portion of the beam is reflected off the substrate's back side surface 412. In silicon, a laser beam having a wavelength of 1064 nanometers loses about a third of it's energy at the semiconductor-air interface due to reflection at the surface. This is due to the index of refraction difference between air and silicon. The transmitted beam 404 passes through silicon substrate 410 and is reflected off a metal contact or metal interconnect line 414 and back out the back side surface of the semiconductor substrate. About one third of the reflected energy 404 is again lost as the beam passes through the back side surface 412 of the semiconductor substrate. Ignoring energy losses due to absorption and scattering effects, the total energy of the transmitted beam 406 is less than half the intensity of the incident beam 402 .
Reflection at the semiconductor back side surface also affects the number of photon emissions which make it across the silicon/air surface interface. Turning again to FIG. 3, in a semiconductor substrate 305 comprising silicon, about one third of the photon emissions 303 are lost due to reflection at the silicon-air interface at surface 304.
The use of optical-based debugging and testing techniques may require a thinning of the backside of the integrated circuit semiconductor in order to offset the effects of absorption in the semiconductor substrate. Thinning of the semiconductor substrate increases the intensity of photon emissions from the integrated circuit by reducing the loss of energy due to absorption in the semiconductor substrate. Significant thinning of the semiconductor substrate, however, could prohibit testing of the integrated circuit at full speed due to device performance degradation and reduced power dissipation through the remaining thinned silicon substrate.
Therefore, what is needed is a method and an apparatus that enhances the use of optical-based techniques used in the debugging and testing of integrated circuits devices through the backside of a semiconductor.